1. Field of the Invention
The present invention relates to a capacitive load drive circuit for selectively driving a plurality of capacitive loads such as EL (electroluminescence) elements.
2. Description of the Related Art
Heretofore, there has been a capacitive load drive circuit for driving a plurality of capacitive loads such as EL elements as shown by, for example, FIG. 4. The drive circuit comprises a high voltage supply unit 31 for generating a voltage CHV suitable for driving EL elements E1 and E2, an output unit 32 for selectively outputting the voltage CHV of the high voltage supply unit 31 to the EL elements E1 and E2, a drive signal generating unit 33 for generating a drive signal EA, EB for driving the output unit 32 and a selecting unit 34 for generating a selecting signal for selecting either of the EL elements E1 and E2 to be driven and controlling the drive signal generating unit 33 to drive the selected EL elements.
The output unit 32 comprises inverters IVA and IVB and a common inverter IVC, each having the same construction. The inverters IVA and IVB and the common inverter IVC each comprise a P-channel MOS transistor P1 and an N-channel MOS transistor N1 having interconnected drains. The inverters form a plurality of output terminals A, B and C. A source of the P-channel MOS transistor P1 is connected to the output terminal CHV of the high voltage supply circuit 1 and a source of the N-channel MOS transistor N1 is connected to a reference terminal VSS (e.g., OV). The P-channel MOS transistor P1 of each of the inverters IVA and IVB and the common inverter IVC is turned ON and OFF by a drive signal the level of which is shifted by a level shifter LS. The N-channel MOS transistor N1 is turned ON and OFF by the drive signal and outputs the voltage generated by the high voltage supply unit 31 from each of the output terminals A, B and C as a drive voltage. There are also parasitic diodes D1 and D2 present across the outputs of the P-channel MOS transistor P1 and the N-channel MOS transistor N1.
One pole of the EL element E1 is connected to the output terminal A and other pole thereof is connected to the output terminal C to thereby form an H bridge circuit with respect to the EL element E1. One pole of the EL element E2 is connected to the output terminal B and other pole thereof is connected to the common output terminal C (hereinafter, referred to as a common output terminal C) to thereby form an H bridge circuit with respect to the EL element E2.
According to a first drive method using the above-described circuit construction, there is a drive method which is characterized by bringing an output terminal of a non-selected EL element, other than the common output terminal, into a high impedance state by means of a selecting signal, even when the output signal is output to the common output terminal, so that a capacitive coupling effect is produced and the non-selected EL element is neither charged nor discharged.
An explanation will be given of operation of the drive circuit of FIG. 4 with reference to the waveform diagrams shown in FIG. 5.
At a point in time after a standby state has ended, the common output terminal C generates a drive voltage C. The phase of the drive voltage C is defined for reference purposes as a positive phase. When the EL element E1 is instructed to turn on by a selecting signal EA output by the selecting unit 34, the output terminal A generates a drive voltage A having a phase inverse to that of the common output terminal C. As a result, the EL element E1 is charged and discharged to thereby turn on. Meanwhile, when the EL element E2 is instructed to turn off by an EL element selecting signal EB, the output terminal B is brought into a high impedance state. Since the EL element is a capacitive load, the potential Bxe2x80x2 at the output terminal B is varied by an amount that the potential variation at the common output terminal C and the EL element E2 is not charged and discharged to thereby turn off.
Further, two EL elements can be simultaneously turned on by making phases of drive voltages of the output terminal A and the output terminal B inverse to the phase of the common output terminal C and two of the EL elements can be turned off by bringing both the output terminal A and the output terminal B into the high impedance state or turning OFF the high voltage supply unit or an IVC power source.
A second drive method for use with the above-described circuit is characterized in that when an EL element is to be turned on, a drive voltage having a phase inverse to the phase of the drive voltage at the common output terminal is output to the output terminal of the selected EL element (other than the common output terminal). When an EL element is to be turned off, a drive voltage having a positive phase relative to the drive voltage of the common output terminal is applied to the output terminal of the selected EL element (other than the common output terminal).
According to the first drive method described above, and as shown in the timing diagrams of FIG. 5, the selecting signals EA and EB non-synchronously supplied to the drive voltages A, B and C are used as signals for switching the drive voltages as they are. Accordingly, there is a high probability that the drive voltage is switched or stopped at a state in which electric charge is stored by the capacitive load. When this occurs and a drive voltage is applied to the common output terminal successively, there is brought about a phenomenon in which electric charge is made to flow or is drawn to the parasitic diodes across the output terminal of the H bridge circuit which is to be brought into the high impedance state. For example, when at timing t of FIG. 5, a state of simultaneously turning on both the EL element E1 and the EL element E2 is switched to a state of in which only one of the EL elements E2 is turned on (i.e., the state of simultaneously turning on the two is changed to the state of turning on one EL element), in the case in which voltage Va of the high voltage supply unit is supplied to both ends of the EL element E1 with the output terminal A as positive, when the drive voltage of the common output terminal C is successively changed to Va, the potential A of the output terminal A becomes 2xc3x97Va by virtue of capacitive coupling of the EL element, and potential difference between the two poles of the EL element E1 becomes larger than the voltage Va generated by the high voltage supply unit. Accordingly, current is made to flow to the parasitic diodes. Also, when the polarity of voltage remaining at the EL element E1 is reversed, the potential difference between the two poles of the EL element E1 similarly becomes xe2x88x922xc3x97Va. Accordingly, current is similarly made to flow to the parasitic diodes.
Therefore, unnecessary charging and discharging is carried out with respect to the EL element, and there is a problem in that a non-selected EL is nonetheless lighted.
Further, according to the second drive method described above, although the drive voltages applied to the two poles of an EL lamp which is turned off are provided with the same phase, there is a problem in that the EL lamp may be slightly lit due to a difference in power of driving signals applied at the output terminal or a slight deviation in timing.
In view of the foregoing problems, it is an object of the present invention to provide a drive system for bringing an output terminal used for supplying drive voltage to a capacitive load into a high impedance state when the capacitive load is caused to stop driving so that the capacitive load is prevented from being unnecessarily driven by the flow of electric charge to parasitic diodes at the output terminal, so that, for example, an EL element serving as a capacitive load is prevented from being turned on.
In order to achieve the above-described object, according to the present invention, there is provided a synchronizing unit which operates such that when an output terminal of one of a plurality of respective capacitive loads is to be brought into a high impedance state in accordance with a selecting signal non-synchronously generated to produce a drive voltage, a timing thereof is synchronized to a timing at which a potential difference between two poles of the capacitive load is nullified.
According to one aspect of the present invention, there is provided a capacitive load drive circuit comprising an output unit including a common output terminal for commonly connecting poles of a plurality of capacitive loads on one side and individual output terminals for respectives of the capacitive loads for connecting poles of the capacitive loads on another side for generating a common drive voltage at a specific frequency at the common output terminal in accordance with a selecting signal used for selecting a respective one of the capacitive loads to be driven, generating a drive voltage having a phase reverse to a phase of the common drive voltage at the individual output terminal corresponding to the selected capacitive load to be driven, and bringing the individual output terminal corresponding to a non-selected capacitive load into a high impedance state, and a synchronizing unit for synchronizing a timing at which the individual output terminal is brought into the high impedance state to a timing at which a potential difference between the two poles of the capacitive load is nullified.
Further, according to another aspect of the present invention, there is provided a capacitive load drive circuit comprising an inverter common to a plurality of capacitive loads for providing a common output terminal for commonly connecting poles of the plurality of capacitive loads on one side by an output terminal thereof, individual inverters for the respective capacitive loads providing individual output terminals connected with poles of the capacitive loads on another side by output terminals thereof, a selecting unit for generating a selecting signal for selecting a capacitive load to be driven, a clock signal generating unit for generating a clock signal at a specific frequency, a drive signal generating unit for generating a first drive signal and a second drive signal having phases inverse to each other based on the clock signal, outputting the first drive signal to the common inverter to drive the common inverter, outputting the second drive signal to the individual inverter corresponding to a selected one of the capacitive loads to be driven based on the selecting signal to thereby drive the inverter, and outputting a stop signal to a non-selected inverter corresponding to a capacitive load not to be driven to thereby bring the individual output terminal of the inverter into a high impedance state. A common drive voltage at the specific frequency is generated at the common output terminal, a drive voltage having a phase inverse to the phase of the common drive voltage is generated at the individual output terminal corresponding to the selected capacitive load to be driven, and the individual output terminal corresponding to the non-selected capacitive load not to be driven is brought into the high impedance state to thereby selectively drive the plurality of capacitive loads. The selecting unit includes a synchronizing unit for generating the selecting signal in synchronism with a timing at which a potential difference between the two poles of the capacitive load is nullified based on the clock signal for bringing the individual output terminal corresponding to the non-selected capacitive load into the high impedance state in synchronism with the timing at which the potential difference between the two poles of the capacitive load is nullified.
Preferably, a plurality of the selecting signals are generated to correspond to the respective capacitive loads in synchronism with the clock signal, the drive signal generating unit generates the first drive signal and the second drive signal in synchronism with the clock signal, the second drive signal is output to the inverter corresponding to the capacitive load in correspondence with the selecting signal during a time period in which the selecting signal is being generated, and the stop signal is output in place of the second drive signal when the selecting signal is interrupted.
Further, it is also preferable that the capacitive load comprises an EL element.